Your first project

Getting the first design to work is always the hardest part. In this chapter we will virtually wire two switches up to two LEDs.

On finishing this chapter you will have:

• Created a new project

• Created a new VHDL module

• Entered basic code

• Implemented the design

• Set which I/O pins will be connected to which internal signals

• Implemented the design again

• Used the hardware programming tool for your board

• Tested the design in hardware

Wow! That is a lot of learning for one sitting!

Step 1 - Create a new Project

This is pretty much a "follow your nose" task, however the target device settings must exactly match the FPGA you are using.

• Click on "Xilinx ISE Design Suite 13.3 Studio" icon. In more recent version you may need to select "Start/Xilinx Design

Tools/ISE Design Suite xx.y/ISE Design tools/64-bit Project Navigator".

• From the "File" menu, choose "New Project"

• Name the project "Switches_LEDs", and click on "Next".

This is the screen where you say what FPGA device you are using. Choose the following settings to tell the design tools what chip you are using (I’m using the 250,000 gate count XC3S250E - if you are using a different one then select XC3S100E or XC3S500E), then press the "Next" button.

For the Papilio One 250

Click on "Next", then click on "Finish" to create and open the new project

Step 2 - Create a new VHDL Module

• Right-click on the design window, on the FPGA device, and choose "New Source"

• Highlight "VHDL module" and in the file name enter "Switches_LEDs", then press the "Next"      button.

• This dialog box allows you to define what connections the module has. We need four connections-- two for the switches and two for the LEDs:

• Click the "Next" button, then "Finish" to create the module and open it in the editor.

Note

     To make things clearer, delete any line that starts with "--". They are just comments that do not influence the design.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Switches_LEDs is

Port ( switch_0 : in STD_LOGIC;

switch_1 : in STD_LOGIC;

LED_0 : out STD_LOGIC;

LED_1 : out STD_LOGIC);

end Switches_LEDs;

architecture Behavioral of Switches_LEDs is

begin

end Behavioral;

As you can see, it has created the definition for an entity called Switches_LEDs, with two inputs and two outputs-- STD_LOGIC is used to indicate what values these inputs and outputs can have.

The architecture section is where you describe how the internal logic of the module actually works. For this project we use the "assignment" operator ("(") to assign the LEDs the values of the switches:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Switches_LEDs is

Port ( switch_0 : in STD_LOGIC;

switch_1

LED_1 : out STD_LOGIC);

end Switches_LEDs;

architecture Behavioral of Switches_LEDs is

begin

LED_0 <= switch_0;

LED_1 <= switch_1;

end Behavioral;

If you press the green "play" arrow in the middle left of the design window, the project should start building.

If your code has been entered successfully, the project will build without any errors, and the design Window will now look like this:

Great!You’ve built your first design! There is only one problem, and that is we haven’t told the design tools which pins to

connect these signals to.

Step 3 - Creating constraints

To tell the tools which physical pins should be connected to the VHDL inputs and outputs we need an "Implementation Constraints

File". Here’s how you add one:

• From the "Project Menu" choose "New Source"

• Select "Implementation Constraints File" and call it "constraints":

• Click "Next" and "Finish"

• In the design window, a small "+" will appear by the Switches_LEDs module. Click that to show the new file:

• Double-click "constraints.ucf" to open it in the editor window

• Add the following lines, which assign locations to the four wires, and instruct the tools to create a design that uses "LVTTL

(Low Voltage Transistor Transistor Logic)" signal levels:

# Constraints for Papilio One

NET switch_1 LOC = "P3" | IOSTANDARD=LVTTL;

NET switch_0 LOC = "P4" | IOSTANDARD=LVTTL;

NET LED_1 LOC = "P16" | IOSTANDARD=LVTTL;

NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL;

# Constraints for Basys2 

NET switch_1 LOC = "L3" | IOSTANDARD=LVTTL;

NET switch_0 LOC = "P11" | IOSTANDARD=LVTTL;

NET LED_1 LOC = "M11" | IOSTANDARD=LVTTL;

NET LED_0 LOC = "M5" | IOSTANDARD=LVTTL;

Save the changes to this file, and then once again click on the Green arrow to build the design.

If that is successful, double-click on "Generate Programming File":

You will now have a .bit file in the project directory that can be used to program the FPGA!

Step 4 - Downloading the design into the device

For the Papilio One, using Windows:

• Connect your board to the USB port

• In Windows Explorer navigate to the project directory and find the "Papilio Bit File"

• Double-click on the file. It will bring up the following Window:

• Just press enter

• The design will be downloaded, and then the board will be configured with your design

For the Papilio One, using Linux

• Connect your board to the USB port.

If you are using a relatively modern distribution, two USB tty devices will be created by your operating system (i.e. /dev/ttyUSB’x’ and /dev/ttyUSB’y’). The x and y will be replaced by numbers. The lowered numbered device will be a conduit the papilio-prog program uses to transfer the bitfile to your Papilio board. The higher numbered device can be used (with a program such as minicom) to connect to your Papilio board via its serial UART if your design included provisions for communicating via the UART (which this project has not).

• From the command line, navigate to the project directory and find your switches_leds.bit bitfile.

• If you placed your papilio-prog program somewhere on your $PATH then all you need to do to load your Papilio board with your bitfile is:

# papilio-prog -b switches_leds.bit

If your papilio-prog program is not along your $PATH, you’ll need to invoke it by prefixing it with its explicit location.

Note that if you receive an error somewhat like the following:

Could not access USB device 0403:6010

It is probably because you need to be the super-user in order to issue the papilio-prog command. You can either fix this by using su to become the super-user or prefixing the command with sudo.

For the Basys2:

• Connect your board to the USB port

• Launch Digilent’s Adept software

• If the device isn’t automatically detected, click on the "Device manager" and add it to the device table.

• Use the browse button to search for your project’s .bit file

• Press the program button, and ignore the warnings about the JTAG clock

• The design will be downloaded, and then the board will be configured with your design

As you move the two rightmost slide switches the two rightmost LEDs should turn off and on. Well done!

Viewing how your design has been implemented

I find it interesting to see what the software tools make of my designs.

If you are keen you are able to view how your design is implemented within the FPGA at three different levels - Register Transfer,

Technology and the Routed Design.

You can find the options to view buried away in the process tree:

Here area few screen shots from some designs:

• The Register Transfer Level (RTL) Schematic, which shows how all your design-level components are connected:

• The Technology Schematic, which shows how the individual components within the FPGA are connected:

• The Routed Design, which shows the physical locations and interconnects that are used on the FPGA chip:

 Note on Xilinx GUI (FPGA Editor) under Linux

The Xilinx "View/Edit Routed Design (FPGA Editor)" tool from ISE 14.2, seems to have been written in C++ and compiled using an older version of the C++ library. In a more modern distribution you’ll probably find you can’t launch this tool. When

you try to launch it the linker will complain about not being able to find the required libraries. If your distribution comes with older "compat" C++ libraries you can install them so this tool can be launched.

For example, on openSUSE 12.2 I installed the

libstdc++33

package in order to get this tool to work.

Note on Papilio Bitfile Downloader under Linux

If you are using Linux, the link for downloading the Papilio Loader (which is given above) will not lead you to find anything you can use to send a bitfile to your Papilio board. At this time there doesn’t seem to exist any GUI-based bitfile downloaders for Linux, but a command-line based version works just fine. To obtain the command-line based program for programming your Papilio board with a bitfile, follow these steps:

$ git clone git://github.com/GadgetFactory/Papilio-Loader.git

$ cd Papilio-Loader/Program

$ ./autogen.sh

$ ./configure

if the previous step complains about:

checking for libftdi... no

configure: error: Package requirements (libftdi >= 0.16) were not met:

No package ’libftdi’ found 

then you need to install the ftdi library development package onto your system. Google around if you don’t know how to dothis for your distribution. Repeat the ./configure command until it completes w ithout error, then

$ make

If your make is successful you’ll now have a papilio-prog program which you can copy to some location on your $PATA.